1. Field of the Invention
Embodiments of the invention are related to semiconductor power converter technology, and in particular, to technology related to constructing multilevel power conversion circuits.
2. Description of the Related Art
FIG. 7 shows an example of seven level power conversion circuit according to a conventional technology disclosed in Japanese Unexamined Patent Application Publication No. H11-164567. The circuit of FIG. 7 is a partial circuit for one phase of a multilevel, seven level in the conventional circuit of FIG. 7, power conversion circuit. A single phase conversion circuit can be composed by using two partial circuits of FIG. 7 and a three phase conversion circuit can be composed by using three partial circuits of FIG. 7. Referring to FIG. 7, a DC power supply assembly BA2 comprises series-connected single DC power supplies b11, b12, b13, b21, b22, and b23. The DC power supply assembly BA2 has seven terminals P1, P2, P3, M, N1, N2, and N3 at seven different voltage levels. A series connection circuit of semiconductor switches Q1 through Q12, which are IGBTs in this example, is connected between the positive terminal P3 and the negative terminal N3. The connection point of the semiconductors Q6 and Q7 is connected to an AC output terminal U. A diode arm pair DA1 composed of series-connected diodes D1 and D2 is connected between the connection point of the semiconductor switches Q1 and Q2 and the connection point of the semiconductor switches Q7 and Q8. The middle terminal of the diode arm pair DA1 is connected to the connection point of the single DC power supplies b11 and b12.
Similarly, a diode arm pair DA2 composed of series-connected diodes D3 and D4 is connected between the connection point of the semiconductor switches Q2 and Q3 and the connection point of the semiconductor switches Q8 and Q9. The middle terminal of the diode arm pair DA2 is connected to the connection point of the single DC power supplies b12 and b13.
A diode arm pair DA3 composed of series-connected diodes D5 and D6 is connected between the connection point of the semiconductor switches Q3 and Q4 and the connection point of the semiconductor switches Q9 and Q10. The middle terminal of the diode arm pair DA3 is connected to the connection point of the single DC power supplies b13 and b21.
The diode arm pair DA4 composed of series-connected diodes D7 and D8 is connected between the connection point of the semiconductor switches Q4 and Q5 and the connection point of the semiconductor switches Q10 and Q11. The middle terminal of the diode arm pair DA4 is connected to the connection point of the single DC power supplies b21 and b22.
A diode arm pair DA5 composed of series-connected diodes D9 and D10 is connected between the connection point of the semiconductor switches Q5 and Q6 and the connection point of the semiconductor switches Q11 and Q12. The middle terminal of the diode arm pair DA5 is connected to the connection point of the single DC power supplies b22 and b23.
In this circuit construction, when the semiconductor switches Q1 through Q6 are in the ON state and the semiconductor switches Q7 through Q12 are in the OFF state, the AC terminal U outputs a voltage +3E; when the semiconductor switches Q2 through Q7 are in the ON state and the semiconductor switches Q8 through Q12 and Q1 are in the OFF state, the AC terminal U outputs a voltage +2E; when the semiconductor switches Q3 through Q8 are in the ON state and the semiconductor switches Q9 through Q12 and Q1 and Q2 are in the OFF state, the AC terminal U outputs a voltage +1E; when the semiconductor switches Q4 through Q9 are in the ON state and the semiconductor switches Q10 through Q12 and Q1 through Q3 are in the OFF state, the AC terminal U outputs a voltage 0 (zero); when the semiconductor switches Q5 through Q10 are in the ON state and the semiconductor switches Q11 and Q12 and Q1 through Q4 are in the OFF state, the AC terminal U outputs a voltage −1E; when the semiconductor switches Q6 through Q11 are in the ON state and the semiconductor switches Q12 and Q1 through Q5 are in the OFF state, the AC terminal U outputs a voltage −2E; and when the semiconductor switches Q7 through Q12 are in the ON state and the semiconductor switches Q1 through Q6 are in the OFF state, the AC terminal U outputs a voltage −3E. Thus, the AC terminal U can deliver seven levels of output voltages by adjusting ON/OFF of the semiconductor switches Q1 through Q12.
In the conventional circuit of FIG. 7, six series-connected semiconductor switches at the maximum carry the output current from the DC power supply assembly BA2 to the AC terminal U. This causes large steady-state ON-state loss in the semiconductor switches and deterioration of the overall conversion efficiency of the conversion device. Down-sizing and cost reduction are also difficult. Additionally in the multilevel power conversion circuit as shown in FIG. 7, the single DC power supplies b11, b12, b13, b21, b22, and b23 do not bear an equal power in principle even though the output voltage and current from the AC terminal U have AC wave forms symmetrical with respect to electrical polarity. Thus, the single DC power supplies need to be independent on each other. The DC power supply assembly BA2, an input device of the multilevel power conversion circuit, needs six single DC power supplies each delivering a power independently, which imposes a severe limitation in production of the device. The problem of unbalance of DC power supplies is disclosed in IEEE-PESC 1995 Conference Record pp. 1144-1150 entitled “A multi-level voltage source converter system with balanced DC voltage.” Thus, as described above, there exists certain shortcomings in the art of DC power supplies.